1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated circuit elements, such as MOS transistor structures, requiring sophisticated lateral and vertical dopant profiles.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling down of transistor elements, such as MOS transistor elements, to provide the great number of transistor elements that may be necessary for producing modern CPUs and memory devices. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. For example, so-called short channel effects may occur for highly scaled transistor elements, resulting in reduced controllability of the channel region, which may result in increased leakage currents and generally in degraded transistor performance. One challenging task in this respect therefore is the provision of appropriately designed junction regions in the form of shallow junctions, at least at the area in the vicinity of the channel region, i.e., source and drain extension regions, which nevertheless exhibit a moderately high conductivity to maintain the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions at a relatively low level while also controlling the parasitic drain/source capacitance and the electric field of the cut off region. The requirement for shallow junctions having a relatively high conductivity while providing adequate channel control is commonly met by performing an ion implantation sequence on the basis of a spacer structure to obtain a high dopant concentration having a profile that varies laterally and in depth. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure, and therefore one or more anneal cycles are typically required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the heavy crystal damage. However, the electrically effective dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants. This ability in turn is limited by the solid solubility of the dopants in the silicon crystal and the temperature and duration of the anneal process that are compatible with the process requirements. Moreover, besides the dopant activation and the curing of crystal damage, dopant diffusion may also occur during the annealing, which may lead to a “blurring” of the dopant profile, which may be advantageous for defining critical transistor properties, such as the overlap between the extension regions and the gate electrode. Therefore, for highly advanced transistors, the positioning, shaping and maintaining of a desired dopant profile are important properties for defining the final performance of the device, since the overall series resistance of the conductive path between the drain and source contacts, as well as the controllability of the channel region, may represent a dominant aspect for determining the transistor performance.
The definition of the effective channel length and the adjustment of the dopant profile to account for short channel behavior on the basis of conventional well-established anneal and implantation techniques may result in a spacer width that is a compromise for different device types, as will be explained in more detail with reference to FIGS. 1a-1e. 
FIG. 1a schematically illustrates a cross-sectional view of a transistor device 100 in an advanced manufacturing stage. The transistor 100 may represent any type of sophisticated field effect transistor as typically used in sophisticated integrated circuits, such as microprocessors, storage chips and the like. The transistor 100 comprises a substrate 101, which may represent any appropriate carrier material for forming thereabove an appropriate semiconductor layer 102, in and above which respective circuit components, such as the transistor 100, are to be formed. For example, the substrate 101 may represent a silicon substrate or any other appropriate material, thereby defining a silicon-on-insulator (SOI) configuration, wherein, in this case, an insulating layer 103 may be provided below the semiconductor layer 102. Furthermore, a gate electrode 105, for instance comprised of polysilicon, may be formed above the semiconductor layer 102 and may be separated therefrom by a gate insulation layer 104. In this manufacturing stage, respective offset spacers 107, which may be comprised of silicon dioxide, silicon oxynitride and the like, are provided with an appropriate thickness 107T, which in turn is selected to define a desired offset of respective extension regions 108E defined by a corresponding dopant species of a specified conductivity type in accordance with the design of the transistor device 100. For instance, for an N-channel transistor, the extension regions 108E may comprise an N-type dopant species.
It should be appreciated that the length of a channel region 106, i.e., in FIG. 1a, the spacing between the extension regions 108E in the horizontal direction, depends on the length of the gate electrode 105 and the spacer width 107T, wherein the actual effective channel length may finally be determined by respective PN junctions formed by the extension regions 108E with the channel region 106. That is, the effective channel length may be adjusted by a controlled diffusion process, as previously explained.
The transistor device 100 as shown in FIG. 1a may be formed on the basis of the following well-established processes. After providing the substrate 101 having formed thereon the buried insulating layer 103 and the semiconductor layer 102, respective isolation structures (not shown), such as shallow trench isolations (STI) and the like, may be formed to define appropriately sized active areas within the semiconductor layer 102, in which one or more circuit components may be formed, such as the transistor 100. For this purpose, sophisticated lithography, etch, deposition and planarization techniques may be used. Subsequently, the doping of the channel region 106 may be adjusted in accordance with transistor requirements. Thereafter, appropriate materials for the gate electrode 105 and the gate insulation layer 104 may be provided, for instance, by oxidation and/or deposition for the gate insulation layer 104 and by deposition of the material of the gate electrode 105, followed by advanced lithography and etch techniques in order to appropriately define the lateral dimensions of the gate electrode 105. For sophisticated applications, the gate length, which also affects the effective channel length, may be in the range of approximately 50 nm and even less for highly advanced semiconductor devices. Next, the offset spacer 107 may be formed on the basis of conformal deposition techniques and/or oxidation processes followed by an etch process, wherein the initial layer thickness and the respective etch conditions may substantially determine the width 107T. Furthermore, an implantation process 110 is performed to introduce the required dopant species for defining the extension regions 108E, wherein a respective offset to the gate electrode 105 may be obtained by the offset spacers 107. It should be appreciated that other implantation processes may be performed, such as a pre-amorphization implantation, a halo implantation and the like, depending on the device requirements.
FIG. 1b schematically illustrates the transistor device 100 in a further advanced manufacturing stage. As shown, a further spacer element 111 may be provided to define, in combination with the offset spacer 107 and a corresponding etch stop layer 112, if provided, a spacer structure 113. The spacer structure 113 may also comprise additional individual spacer elements (not shown), depending on the respective process requirements. The spacer element 111 may be comprised of any appropriate material, such as silicon nitride, and may have a width adapted to define deep drain and source portions 108D formed by a respective implantation process 114. For driving the deep drain and source regions 108D towards a desired depth, for instance, towards the buried insulating layer 103, the corresponding lateral diffusion may also have to be accommodated by the spacer width 111W. Thus, the overall width of the spacer structure 113 may be correlated with the overall configuration of the drain and source regions comprising the extension region 108E and the deep drain and source region 108D, wherein the spacer width 111W and the thickness 107T (FIG. 1a) may also be correlated in order to obtain a desired effective channel length and an appropriate dopant profile for the desired performance characteristics after a corresponding anneal process.
FIG. 1c schematically illustrates the transistor device during a corresponding anneal process 115, wherein respective process parameters, that is, the effective anneal temperature and the duration of the process, may be selected such that desired lateral and vertical profiles of the drain and source regions 108D, 108E (FIG. 1b) are obtained.
However, sophisticated semiconductor devices typically comprise a plurality of different circuit elements, which may be formed in accordance with a well-established common manufacturing sequence, while the final performance of the circuit elements may differ significantly from each other so that the dopant profile obtained during the above-described process sequence may not result in optimum performance of each of the different circuit elements. For example, using the above-described conventional strategy for establishing an appropriate profile for transistor elements, such as PMOS transistors and NMOS transistors, or obtaining dopant profiles for different circuit architectures, such as analog or digital circuits, may require selecting the respective process parameters and dimensions of device features to obtain a dopant profile that meets the requirements for any of these different transistor elements. For example, the adjustment of certain transistor characteristics, such as high threshold voltage or low threshold voltage, the type of dopant used in order to obtain the appropriate conductivity type and the like, may be accomplished on the basis of various masking and implant sequences wherein, however, the fundamental positioning of the dopant may not be efficiently changed according to the above-described conventional process strategy. In a recent technology development, transistor performance of sophisticated CMOS devices may be enhanced by providing an appropriate semiconductor alloy, such as silicon/germanium, in the drain and source regions of the transistors in order to create a desired type of strain in the adjacent channel region. Due to the induced strain, the charge carrier mobility may be increased in the channel region, thereby compensating for certain mobility degradation effects that may have been created in an attempt to reduce short channel effects. Furthermore, based on a specific channel length, the overall transistor performance may be increased for a given technology standard since an increased charge carrier mobility directly translates into an increased current drive capability and thus increased operating speed of the transistor. However, providing silicon/germanium alloy in a significant portion of the drain and source regions of a P-channel transistor may have a significant influence on the finally obtained dopant profiles, since, for instance, the diffusivity of certain P-type dopants, such as boron, may be significantly less in the presence of a moderately high germanium concentration compared to the boron diffusion in a silicon material. Consequently, when P-channel transistors of substantially conventional design and high speed P-channel transistors are to be provided in the same semiconductor device, the above-described conventional manufacturing process may have to take into consideration further types of transistor devices, as will be described in more detail with reference to FIGS. 1d-1e. 
FIG. 1d schematically illustrates the semiconductor device 100 for this case. A first transistor 100A and a second transistor 100B may be provided in different device regions and may represent P-channel transistors requiring a different type of performance behavior. For instance, the transistor 100A may represent a transistor in a device region requiring low leakage behavior while the switching speed may not be as essential as for the second transistor 100B. In principle, the transistors 100A, 100B may have the same configuration as the transistor 100 as shown in FIGS. 1a-1c, except for a silicon/germanium alloy 116 formed in a portion of the semiconductor layer 102 (FIG. 1c), in which drain and source regions are to be formed on the basis of a respective implantation process 117. As explained above, the implantation parameters, in combination with the overall transistor configuration, may be selected such that a compromise may be obtained after the implantation process 117 for the drain and source regions 108 to obtain a moderately high performance for the transistor 100A and for the transistor 100B.
FIG. 1e schematically illustrates the semiconductor device 100 during the anneal process 115 for finally defining the dopant profile of the drain and source regions 108, for instance, in view of defining an effective channel length, as previously explained. Due to the reduced diffusivity of boron, which may be introduced during the implantation process 117, the vertical and lateral diffusion length in the transistor 100B may be reduced compared to the device 100A, thereby resulting in non-optimal dopant profiles or obtaining an optimized dopant profile for one of the transistors 100A, 100B, while significantly reducing device performance for the other one of the transistors 100A, 100B. For instance, as shown in FIG. 1e, the transistor 100a may have a desired dopant profile for reducing the overall drain/source resistance with a moderate parasitic capacitance, while the transistor 100B may exhibit an increased source/drain resistance for the benefit of a reduced drain/source capacitance, thereby possibly offsetting to a certain degree the performance gain obtained by the provision of the strained silicon/germanium alloy 116.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.